The subject matter disclosed herein relates to the fabrication of field effect transistors (FETs). More specifically, embodiments of the present disclosure relate to methods of forming integrated circuit (IC) structures which use a boron layer used as an etch stop, and resulting IC structures which include a boron-rich region for transistors to electrically connect contacts to source and drain terminals.
In integrated circuit (IC) structures, a transistor is a critical component for implementing digital circuitry designs. Generally, a transistor includes three electrical terminals: a source, a drain, and a gate. By applying different voltages to the gate terminal, the flow of electric current between the source and the drain can be turned on and off. The gate of a transistor can be formed as a gate stack structure (i.e., a “metal gate stack”) composed of a metal separated from a semiconductor element by a gate dielectric layer. Two processing paradigms for fabricating a gate stack can include a gate-first approach or a gate-last approach. The gate-last approach can also be known as a “replacement metal gate” (RMG) process flow, in which other portions of the transistor (e.g., source and drain contacts, channel region, etc.) are formed using a dummy gate structure that is replaced with the final gate after fabrication of other parts. The performance of transistors formed through an RMG process is at least partially dependent on the various processes applied during manufacture. For example, the amount of electrical conductivity and resistance between a contact to the transistor and the various components and regions thereof can affect quantities such as operating speed, manufacturing quality, variance between units, degradation of materials over time, etc.